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?2005 fairchild semiconductor corporation www.fairchildsemi.com rev.1.0.8 fps tm is a trademark of fairchild semiconductor corporation. features ? internal avalanche rugged sense fet ? consumes only 0.65w at 240vac & 0.3w load with advanced burst-mode operation ? frequency modulation for emi reduction ? precision fixed operating frequency ? internal start-up circuit ? pulse-by-pulse current limiting ? abnormal over current protection (aocp) ? over voltage protection (ovp) ? over load protection (olp) ? internal thermal shutdown function (tsd) ? auto-restart mode ? under voltage lockout (uvlo) ? low operating current (3ma) ? adjustable peak current limit ? built-in soft start applications ? smps for vcr, svr, stb, dvd & dvcd player ? smps for printer, facsimile & scanner ? adapter for camcorder related application notes ? an-4137, 4141, 4147(flyback) / an-4134(forward) description each product in the fsdx0365rn (x for l, m) family consists of an integrated pulse width modulator (pwm) and sense fet, and is specifically design ed for high performance off-line switch mode power supplies (s mps) with minimal external components. both devices are integrated high voltage power switching regulators which combine an avalanche rugged sense fet with a current mode pwm control block. the inte- grated pwm controller features include: a fixed oscillator with frequency modulation for reduced emi, under voltage lock out (uvlo) protection, leading edge blanking (leb), an optimized gate turn-on/turn-off driver, thermal shut down (tsd) protection, abnormal over current protection (aocp) and temperature compensated precision current sources for loop compensation and fault prot ection circuitry. when com- pared to a discrete mosfet a nd controller or rcc switching converter solution, the fsdx0365rn devices reduce total component count, design size, weight while increasing effi- ciency, productivity and system reliability. both devices pro- vide a basic platform that is well suited for the design of cost- effective flyback converters. notes : 1. typical continuous powe r in a non-ventilated enclosed adapter with sufficient drain pattern as a heat sinker, at 50 c ambient. 2. maximum practical continuous power in an open frame design with sufficient drain pattern as a heat sinker, at 50 c ambient. 3. 230 vac or 100/115 vac with doubler. typical circuit output power table product 230vac 15% (3) 85-265vac adapt- er (1) open frame (2) adapt- er (1) open frame (2) fsdl321 11w 17w 8w 12w fsdh321 11w 17w 8w 12w fsdl0165rn 13w 23w 11w 17w fsdm0265rn 16w 27w 13w 20w fsdh0265rn 16w 27w 13w 20w fsdl0365rn 19w 30w 16w 24w fsdm0365rn 19w 30w 16w 24w fsdl321l 11w 17w 8w 12w fsdh321l 11w 17w 8w 12w fsdl0165rl 13w 23w 11w 17w fsdm0265rl 16w 27w 13w 20w fsdh0265rl 16w 27w 13w 20w fsdl0365rl 19w 30w 16w 24w fsdm0365rl 19w 30w 16w 24w drain source vstr vfb vcc pwm ac in dc out ipk fsdl0365rn, fsdm0365rn green mode fairchild power switch (fps tm )
fsdl0365rn, fsdm0365rn 2 figure 1. typical flyback application internal block diagram figure 2. functional block diagram of fsdx0365rn 8v/12v 2 6,7,8 1 3 vref internal bias s q q r osc vcc vcc i delay i fb v sd tsd vovp vcc vocp s q q r r 2.5r vcc good vcc drain vfb gnd aocp gate driver 5 vstr i ch vcc good v burl /v burh leb pwm + - 4 ipk freq. modulation v burh vcc i bur(pk) burst normal soft start
fsdl0365rn, fsdm0365rn 3 pin definitions pin configuration figure 3. pin confi guration (top view) pin number pin name pin function description 1 gnd sense fet source terminal on primary side and internal control ground. 2vcc positive supply voltage input. although connected to an auxiliary transform- er winding, current is supplied from pi n 5 (vstr) via an internal switch during startup (see internal block diagram sect ion). it is not until vcc reaches the uvlo upper threshold (12v) that the internal start-up switch opens and de- vice power is supplied via the auxiliary transformer winding. 3vfb the feedback voltage pin is the non-inverting input to the pwm comparator. it has a 0.9ma current source connected internally while a capacitor and op- tocoupler are typically connected externally. a feedback voltage of 6v trig- gers over load protection (olp). there is a time delay while charging external capacitor cfb from 3v to 6v using an internal 5ua current source. this time delay prevents false triggering under transient conditions, but still allows the protection mechanism to operate under true overload conditions. 4ipk this pin adjusts the peak current limit of the sense fet. the feedback 0.9ma current source is diverted to the parallel combination of an internal 2.8k ? resistor and any external resistor to gnd on this pin to determine the peak current limit. if this pin is tied to vcc or left floating, the typical peak cur- rent limit will be 2.15a. 5vstr this pin connects directly to the rectified ac line voltage source. at start up the internal switch supplies internal bias and charges an external storage capacitor placed between the vcc pin and ground. once the vcc reaches 12v, the internal switch is opened. 6, 7, 8 drain the drain pins are designed to connect di rectly to the primary lead of the transformer and are capable of switching a maximum of 650v. minimizing the length of the trace connecting these pins to the transformer will decrease leakage inductance. 1 2 3 45 6 7 8 gnd vcc vfb ipk vstr drain drain drain 8dip 8lsop
fsdl0365rn, fsdm0365rn 4 absolute maximum ratings (ta=25 c, unless otherwise specified) note: 1. repetitive rating: pulse width is limit ed by maximum junction temperature 2. l = 51mh, starting tj = 25 c thermal impedance (ta=25 c, unless otherwise specified) note: 1. free standing with no heatsink; without copper clad. / measurement conditi on : just before j unction temperature t j enters into otp. 2. measured on the drain pin close to plastic interface. 3. measured on the pkg top surface. - all items are tested with the st andards jesd 51-2 and 51-10 (dip). characteristic symbol value unit drain pin voltage v drain 650 v vstr pin voltage v str 650 v drain current pulsed (1) i dm 12.0 a single pulsed avalanche energy (2) e as 127 mj supply voltage v cc 20 v feedback voltage range v fb -0.3 to v cc v total power dissipation p d 1.56 w operating junction temperature t j internally limited c operating ambient temperature t a -25 to +85 c storage temperature t stg -55 to +150 c parameter symbol value unit 8dip junction-to-ambient thermal (1) ja 80.01 c/w junction-to-case thermal (2) jc 18.85 c/w junction-to-top thermal (3) jt 33.70 c/w
fsdl0365rn, fsdm0365rn 5 electrical characteristics (ta = 25 c unless otherwise specified) note : 1. pulse test: pulse width 300us, duty 2% 2. these parameters, although guaranteed, ar e tested in eds (wafer test) process 3. these parameters, although guaranteed, are not 100% tested in production parameter symbol condition min. typ. max. unit sense fet section zero-gate-voltage drain current i dss v ds =650v, v gs =0v - - 50 a v ds =520v, v gs =0v, t c =125 c - - 200 a drain-source on-state resistance (1) r ds(on) v gs =10v, i d =0.5a - 3.6 4.5 ? input capacitance c iss v gs =0v, v ds =25v, f=1mhz - 315 - pf output capacitance c oss -47- pf reverse transfer capacitance c rss -9- pf turn-on delay time t d(on) v ds =325v, i d =1.0a - 11.2 - ns rise time t r - 34 - ns turn-off delay time t d(off) - 28.2 - ns fall time t f - 32 - ns control section switching frequency f osc fsdm0365r 61 67 73 khz switching frequency modulation ? f mod 1.5 2.0 2.5 khz switching frequency f osc fsdl0365r 45 50 55 khz switching frequency modulation ? f mod 1.0 1.5 2.0 khz switching frequency variation (2) ? f osc -25 c ta 85 c - 5 10 % maximum duty cycle d max 71 77 83 % minimum duty cycle d min 000% uvlo threshold voltage v start v fb =gnd 11 12 13 v v stop v fb =gnd 7 8 9 v feedback source current i fb v fb =gnd 0.7 0.9 1.1 ma internal soft start time t s/s v fb =4v 10 15 20 ms burst mode section burst mode voltage v burh - 0.4 0.5 0.6 v v burl - 0.25 0.35 0.45 v protection section peak current limit i lim max. inductor current 1.89 2.15 2.41 a current limit delay time (3) t cld - 500 - ns thermal shutdown temperature t sd - 125 140 - c shutdown feedback voltage v sd 5.5 6.0 6.5 v over voltage protection v ovp 18 19 - v shutdown delay current i delay v fb =4v 3.5 5.0 6.5 a leading edge blanking time t leb 200 - - ns total device section operating supply current (control part only) i op v cc =14v 1 3 5 ma start-up charging current i ch v cc =0v 0.7 0.85 1.0 ma vstr supply voltage v str v cc =0v 35 - - v
fsdl0365rn, fsdm0365rn 6 comparison between ka 5x0365rn and fsdx0365rn function ka5x0365rn fsdx0365rn fsdx0365rn advantages soft-start not applicable 15ms ? gradually increasing current limit during soft-start further reduces peak current and voltage stresses ? eliminates external components used for soft-start in most applications ? reduces or eliminates output overshoot external current limit not applicable programmable of default current limit ? smaller transformer ? allows power limiting (constant over- load power) ? allows use of larger device for lower losses and higher efficiency. frequency modulation not applicable 2.0khz @67khz 1.5khz @50khz ? reduces conducted emi burst mode operation not applicable built into controller ? improves light load efficiency ? reduces power consumption at no- load ? transformer audible noise reduction drain creepage at package 1.02mm 7.62mm ? greater imm unity to arcing provoked by dust, debris and other contami- nants
fsdl0365rn, fsdm0365rn 7 typical performance char acteristics (control part) ( these characteristic graphs are normalized at ta = 25 c) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized operating frequency (fosc) vs. ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized frequency modulation ( ? f mod ) vs. ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized maximum duty cycle (d max ) vs. ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized operating supply current (i op ) vs. ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized start threshold voltage (v start ) vs. ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized stop threshold voltage (v stop ) vs. ta
fsdl0365rn, fsdm0365rn 8 typical performance characteristics (continued) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized feedback source current (i fb ) vs. ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized peak current limit (i lim ) vs. ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized start up charging current (i ch ) vs. ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized burst peak current (i bur(pk) ) vs. ta 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -50 0 50 100 150 temp[ ] normalized over voltage protection (v ovp ) vs. ta
fsdl0365rn, fsdm0365rn 9 functional description 1. startup : in previous generations of fairchild power switches (fps tm ) the vstr pin had an external resistor to the dc input voltage line. in this generation the startup resistor is replaced by an internal high voltage current source and a switch that shuts off when 15ms goes by after the supply voltage, vcc, gets above 12v. the source turns back on if vcc drops below 8v. figure 4. high voltage current source 2. feedback control : the fsdx0365rn employs current mode control, as shown in fi gure 5. an opto-coupler (such as the h11a817a) and shunt regulator (such as the ka431) are typically used to implement the feedback network. com- paring the feedback voltage with the voltage across the rsense resistor plus an offset voltage makes it possible to control the switching duty cycle. when the ka431 reference pin voltage exceeds the internal reference voltage of 2.5v, the optocoupler led current increases, the feedback voltage vfb is pulled down and it reduces the duty cycle. this event typically happens when the input voltage is increased or the output load is decreased. figure 5. pulse width m odulation (pwm) circuit 3. leading edge blanking (leb) : at the instant the inter- nal sense fet is turned on, the primary side capacitance and secondary side rectifier diode reverse recovery typically cause a high current spike through the sense fet. excessive voltage across the rsense resistor leads to incorrect feedback operation in the current mode pwm control. to counter this effect, the fps employs a leading edge blanking (leb) cir- cuit. this circuit inhibits the pwm comparator for a short time (t leb ) after the sense fet is turned on. 4. protection circuits : the fps has several protective functions such as over load protection (olp), over voltage protection (ovp), abnormal over current protection (aocp), under voltage lock out (uvlo) and thermal shut- down (tsd). because these protection circuits are fully inte- grated inside the ic without external components, the reliability is improved without increasing cost. once a fault condition occurs, switching is terminated and the sense fet remains off. this causes vcc to fall. when vcc reaches the uvlo stop voltage v stop (8v), the protection is reset and the internal high voltage current source charges the vcc capacitor via the vstr pin. when vcc reaches the uvlo start voltage v start (12v), the fps resumes its normal operation. in this manner, the auto-restart can alternately enable and disable the switching of the power sense fet until the fault condition is eliminated. 4.1 over load protection (olp) : overload is defined as the load current exceeding a pre-set level due to an unex- pected event. in this situation, the protection circuit should be activated in order to protect the smps. however, even when the smps is operating normally, the over load protec- tion (olp) circuit can be activated during the load transition. in order to avoid this undesired operation, the olp circuit is designed to be activated after a specified time to determine whether it is a transient situation or an overload situation. in conjunction with the ipk current limit pin (if used) the cur- rent mode feedback path would limit the current in the sense fet when the maximum pwm duty cycle is attained. if the output consumes more than this maximum power, the output voltage (vo) decreases below its rating voltage. this reduces the current through the opto-coupler led, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (v fb ). if v fb exceeds 3v, the feed- back input diode is blocked and the 5ua current source (i de- lay ) starts to charge cfb slowly up to vcc. in this condition, v fb increases until it reaches 6v, when the switching opera- tion is terminated as shown in figure 6. the shutdown delay time is the time required to charge cfb from 3v to 6v with 5ua current source. vin,dc vstr vcc 15ms after vcc 12v uvlo off vcc<8v uvlo on i str j-fet i ch 3 osc vcc vcc 5ua 0.9ma v sd r 2.5r gate driver olp d1 d2 v fb vfb 431 c fb vo + - v fb,in
fsdl0365rn, fsdm0365rn 10 figure 6. over load protection (olp) 4.2 thermal shutdown (tsd) : the sense fet and the control ic are integrated, making it easier for the control ic to detect the temperature of the sense fet. when the tem- perature exceeds approximately 140 c, thermal shutdown is activated. 4.3 abnormal over current protection (aocp) : even though the fps has olp (over load protection) and current mode pwm feedback, these are not enough to protect the fps when a secondary side diode short or a transformer pin short occurs. in addition to start-up, soft-start is also activated at each restart attempt during auto-restart and when restarting after latch mode is activated. the fps has an internal aocp (abnormal over current protection) circuit, as shown in figure 7. when the gate turn-on signal is applied to the power sense fet, the aocp block is enabled and monitors the current through the sensing resistor. the voltage across the resistor is then compared with a preset aocp level. if the sensing resistor voltage is greater than the aocp level, pulse-by-pulse aocp is triggered regardless of uncontrollable leb time . here, pulse-by-pulse aocp stops the sense fet within 350ns after it is activated. figure 7. abnormal over current protection (aocp) 4.4 over voltage protection (ovp) : in the event of a mal- function in the secondary side feedback circuit, or an open feedback loop caused by a soldering defect, the current through the opto-coupler transistor becomes almost zero (refer to figure 5). then, v fb climbs up in a similar manner to the over load situation, forcing the preset maximum cur- rent to be supplied to the smps until the over load protection is activated. because excess energy is provided to the output, the output voltage may exceed the rated voltage before the over load protection is activated, resulting in the breakdown of the devices in the secondary side. in order to prevent this situation, an over voltage protection (ovp) circuit is employed. in general, vcc is proportional to the output volt- age and the fps uses vcc instea d of directly monitoring the output voltage. if v cc exceeds 19v, ovp circuit is activated resulting in termination of the switching operation. in order to avoid undesired activation of ovp during normal opera- tion, vcc should be properly designed to be below 19v. v fb t 3v 6v over load protection t 12 = c fb (v(t 2 )-v(t 1 )) / i delay t 1 t 2 v t v v t v a i i t v t v c t delay delay fb 6 ) ( , 3 ) ( , 5 ; ) ( ) ( 2 1 1 2 12 = = = ? = vsense v fb,in gate driver rsense clk drain v aocp pwm comparator aocp comparator leb r sq
fsdl0365rn, fsdm0365rn 11 5. soft start : the fps has an internal soft start circuit that slowly increases the feedback voltage together with the sense fet current after it starts up. the typical soft start time is 15msec, as shown in figure 8, where progressive increments of the sense fet current are allowed during the start-up phase. the pulse width to the power switching device is progressively increas ed to establish the correct working conditions for transformers, inductors, and capaci- tors. the voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. it also helps to prevent transformer saturation and reduce the stress on the secondary diode. figure 8. soft start function 6. burst operation : in order to minimize power dissipation in standby mode, the fps enters burst mode operation. as the load decreases, the feedback voltage decreases. as shown in figure 9, the device automatically enters burst mode when the feedback voltage drops below v burh (500mv). switching still continues but the current limit is set to a fixed limit internally to minimize flux density in the transformer. the fixed current limit is larger than that defined by v fb = v burh and therefore, v fb is driven down further. switching continues until the feedback voltage drops below v burl (350mv). at this point switching stops and the output voltages start to drop at a rate dependent on the standby current load. this causes the feedback voltage to rise. once it passes v burh (500mv), switching resumes. the feedback voltage then falls and the process repeats. burst mode operation alternately enables and disables switching of the power sense fet thereby reducing switch- ing loss in standby mode. figure 9. burst operation function 7. frequency modulation : modulating the switching fre- quency of a switched power supply can reduce emi. fre- quency modulation can reduce emi by spreading the energy over a wider frequency range than the bandwidth measured by the emi test equipment. the amount of emi reduction is directly related to the depth of the reference frequency. as can be seen in figure 10, the frequency changes from 65khz to 69khz in 4ms for the fsdm0365rn (48.5khz to 51.5khz for fsdl0365rn). frequency modulation allows the use of a cost effective inductor instead of an ac input mode choke to satisfy the requirements of world wide emi limits. figure 10. frequency modulation waveform 1ms 15steps current limit 0.98a 2.15a t drain current v burh switching off current waveform burst operation normal operation v fb v burl switching off burst operation 3 vcc vcc i delay i fb r 2.5r vfb v burl /v burh pwm + - v burh vcc i bur(pk) burst normal mosfet current t s f s =1/t s 67khz 69khz 65khz 4ms t drain current
fsdl0365rn, fsdm0365rn 12 figure 11. ka5-series fps full range emi scan(67khz, no frequency modulation) with dvd player set figure 12. fsdx-series fps full range emi scan (67khz, with frequency modulati on) with dvd player set 8. adjusting peak current limit : as shown in figure 13, a combined 2.8k ? internal resistance is connected to the non-inverting lead on the pwm comparator. a external resistance of rx on the current limit pin forms a parallel resistance with the 2.8k ? when the internal diodes are biased by the main current source of 900ua. figure 13. peak current limit adjustment for example, fsdx0365rn has a typical sense fet peak current limit (i lim ) of 2.15a. i lim can be adjusted to 1.5a by inserting rx between the ipk pin and the ground. the value of the rx can be estimated by the following equations: 2.15a : 1.5a = 2.8k ? : xk ? , x = rx || 2.8k ? . (x represents the resistance of the parallel network) frequency (mhz) amplitude (db v) frequency (mhz) amplitude (db v) 3 vcc vcc i delay i fb 2k vfb pwm comparator 4 ipk 0.8k rx sensefet current sense 900ua 5ua
fsdl0365rn, fsdm0365rn 13 application tips 1. methods of reducing audible noise switching mode power converters have electronic and magnetic components, which generate audible noises when the operating frequency is in the range of 20~20,000 hz. even though they operate above 20 khz, they can make noise depending on the load condition. designers can employ several methods to reduce these noises. here are three of these methods: glue or varnish the most common method involves using glue or varnish to tighten magnetic components. the motion of core, bobbin and coil and the chattering or magnetostriction of core can cause the transformer to produce audible noise. the use of rigid glue and varnish helps reduce the transformer noise. but, it also can crack the core. this is because sudden changes in the ambient temperature cause the core and the glue to expand or shrink in a different ratio according to the temperature. ceramic capacitor using a film capacitor instead of a ceramic capacitor as a snubber capacitor is another noise reduction solution. some dielectric materials show a piezoelectric effect depending on the electric field intensity. hence, a snubber capacitor becomes one of the most significant sources of audible noise. it is considerable to use a zener clamp circuit instead of an rcd snubber for higher efficiency as well as lower audible noise. adjusting sound frequency moving the fundamental frequency of noise out of 2~4 khz range is the third method. generally, humans are more sensi- tive to noise in the range of 2~4 khz. when the fundamental frequency of noise is located in this range, one perceives the noise as louder although the noise intensity level is identical. refer to figure 14. equal loudness curves. when fps acts in burst mode and the burst operation is suspected to be a source of noise, this method may be help- ful. if the frequency of burst mode operation lies in the range of 2~4 khz, adjusting feedback loop can shift the burst operation frequency. in order to reduce the burst oper- ation frequency, increase a feedback gain capacitor (c f ), opto-coupler supply resistor (r d ) and feedback capacitor (c b ) and decrease a feedback gain resistor (r f ) as shown in figure 15. typical feedback network of fps. figure 14. equal loudness curves figure 15. typical feedback network of fps 2. other reference materials an-4134 : design guidelines for off-line forward convert- ers using fairchil d power switch (fps tm ) an-4137 : design guidelines for off-line flyback convert- ers using fairchild power switch (fps) an-4140 : transformer design consideration for off-line flyback converters using fairchild power switch (fps tm ) an-4141 : troubleshooting and design tips for fairchild power switch (fps tm ) flyback applications an-4147 : design guidelines for rcd snubber of flyback an-4148 : audible noise reduction techniques for fps applications
fsdl0365rn, fsdm0365rn 14 typical application circuit features ? high efficiency (>76% at universal input) ? low standby mode power consumption (<1w at 230vac input and 0.6w load) ? low component count ? enhanced system reliability through various protection functions ? low emi through frequency modulation ? internal soft-start (15ms) key design notes ? the delay time for over load protection is designed to be about 30ms with c106 of 47nf. if faster/slower triggering of olp is required, c106 can be changed to a smaller/larger value(eg. 100nf for about 60ms). ? using a resistor r104(39 ? ) on ipk pin (#4), the pule-by-pulse peak current limit level(i lim ) is adjusted to about 2a. ? the branch formed by d103, c108 and r106 provides another i lim adjustment having a negative slope to the input voltage. the i lim value decreases as the input voltage level increases. 1. schematic application output power input vo ltage output voltage (max current) dvd player 21w universal input (85-265vac) 3.3v (1.0a) 5.1v (0.8a) 12v (0.5a) 16v (0.5a) 3 4 c102 100nf ac275v lf101 55mh c101 100nf ac275v f101 fuse c103 47uf 400v r102 56k ? c104 3.3nf 630v d101 uf 4007 ic101 fsdm0365rn c107 47nf 50v c106 47uf 50v d102 uf 4004 r103 5 ? 1 2 3 4 5 8 9 6 12 10 11 t101 eer2828 d203 egp20d c205 470uf 35v c206 470uf 35v l203 10uh l207 4.7uh l206 4.7uh d204 egp20d c207 470uf 35v c208 470uf 35v c214 1000uf 10v c213 1000uf 10v d207 sb360 d205 sb360 c209 1000uf 10v c210 1000uf 10v r201 510 ? r202 1k ? r203 6.2k ? r204 20k ? c215 100nf r205 6k ? ic302 fod817a bd101 l205 10uh vstr ipk vfb vcc drain gnd 6 1 2 3 4 5 1 2 drain drain 7 8 ic301 ka431 16v r104 39k ? tnr r105 200k ? r106 300k ? d103 uf 4004 c108 1uf 100v c302 2.2nf 12v 5.1v 3.3v rt101 5d-9
fsdl0365rn, fsdm0365rn 15 2. transformer schematic diagram 3. winding specification 4. electrical characteristics 5. core & bobbin core : eer2828 ( ae = 86.66 mm 2 ) bobbin : eer2828 eer2828 n 12v 1 6 7 8 9 10 11 12 n 16v n 5.1v n 3.3v n p /2 n a 2 3 4 5 n p /2 6mm 3mm n 16v n 12v n a n 5.1v n 3.3v n p /2 n p /2 pin(s f) wire turns winding method n p /2 3 2 0.25 1 50 center solenoid winding insulation : polyester tape t = 0.050m m , 2layers n 3.3v 9 8 0.33 2 4 center solenoid winding insulation : polyester tape t = 0.050m m , 2layers n 5.1v 6 9 0.33 1 2 center solenoid winding insulation : polyester tape t = 0.050m m , 2layers n a 4 5 0.25 1 16 center solenoid winding insulation : polyester tape t = 0.050m m , 2layers n 12v 10 12 0.33 1 14 center solenoid winding insulation : polyester tape t = 0.050m m , 3layers n 16v 11 12 0.33 1 18 center solenoid winding insulation : polyester tape t = 0.050m m , 2layers n p /2 2 1 0.25 1 50 center solenoid winding insulation : polyester tape t = 0.050m m , 2layers pin spec. remark inductance 1 3 1.4 mh 10% 100khz, 1v leakage 1 3 25 uh max. short all other pins
fsdl0365rn, fsdm0365rn 16 6. demo circuit part list part value note part value note resistor inductor r102 56k 1w l203 10uh - r103 5 1/4w l205 10uh - r104 39k 1/4w l206 4.7uh - r105 200k 1/4w l207 4.7uh - r106 300k 1/4w diode r201 510 1/4w d101 uf4007 pn ultra fast r202 1k 1/4w d102 uf4004 pn ultra fast r203 6.2 k 1/4w d103 uf4004 pn ultra fast r204 20k 1/4w d203 egp20d pn ultra fast r205 6k 1/4w d204 egp20d pn ultra fast capacitor d205 sb360 schottky c101 100nf/275ac box d207 sb360 schottky c102 100nf/275ac box ic c103 47uf/400v electrolytic ic101 fsdm0365rn fps? c104 3.3nf/630v film ic301 ka431(tl431) voltage reference c106 47uf/50v electrolytic ic302 fod817a opto-coupler c107 47nf/50v ceramic c108 1uf/100v electrolytic fuse c205 470uf/35v electrolytic fuse 2a/250v c206 470uf/35v electrolytic c207 470uf/35v electrolytic ntc c208 470uf/35v electrolytic rt101 5d-9 c209 1000uf/10v electrolytic c210 1000uf/10v electrolytic bridge diode c213 1000uf/10v electrolytic bd101 2kbp06m 2n257 bridge diode c214 1000uf/10v electrolytic c215 100nf/50v ceramic line filter c302 2.2nf ac ceramic lf101 55mh -
fsdl0365rn, fsdm0365rn 17 7. layout 7.1 top image of pcb 7.2 bottom image of pcb
fsdl0365rn, fsdm0365rn 18 package dimensions 8dip
fsdl0365rn, fsdm0365rn 19 package dimensions (continued) 8lsop
fsdl0365rn, fsdm0365rn 9/29/05 0.0m 001 ? 2005 fairchild semiconductor corporation life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain li fe, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. ordering information product number package marking code bv dss f osc r ds(on) fsdm0365rn 8dip dm0365r 650v 67khz 3.6 ? fsdl0365rn 8dip dl0365r 650v 50khz 3.6 ? fsdm0365rl 8lsop dm0365r 650v 67khz 3.6 ? fsdl0365rl 8lsop dl0365r 650v 50khz 3.6 ?

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